Design and Verification using Verilog

About The Course

This course is targeted at both design and verification engineers. The assignments enable students to participate in thought-provoking and practical lab sessions that will be executed from scratch with instructor guidance. The course is strongly recommended for every electronic and electrical core domain student.

This internship is highly recommended for students specializing in the core domains of electronics engineering. This recommendation implies that it is beneficial for students pursuing a comprehensive understanding of electronic systems, circuit design, and verification methodologies.

By participating in this internship, students can expect to enhance their design and verification skills, gain hands-on experience, and develop a deeper understanding of the principles and practical aspects of electronic engineering. Whether students aim to become design engineers or verification engineers, this internship can provide valuable knowledge and practical skills necessary for their respective roles in the field.

What Will You Learn?

Participants will gain expertise in modeling digital blocks using Verilog and performing functional simulation. By the end of the course, learners will enhance their understanding through quizzes and assignments designed to reinforce industry-relevant coding techniques. This course lays a strong foundation for aspiring Digital Design and Verification Engineers.

Key Features of the Course

• Learn Verilog from Scratch
• Design Digital Circuits
• Verification Techniques
• Cadence EDA Tool Access*
• Simulation and Debugging
• Certification and Technical Support