Design Of 2-To-4 Decoder Using Cadence EDA

Prelude :

• Brief overview of digital design flow in Cadence
• Importance of decoder circuits in digital systems
• Gate-level implementation overview
• Writing and applying SDC constraints for Pure combinational circuits

Agenda :

• Writing synthesizable Verilog code for 2-to-4 decoder
• Simulation using Xcelium/Incisive
• Running synthesis
• Viewing synthesis reports (area, timing, etc.)
• Implementation in Innovus
• Q&A

 

Tools Used : Xcelium/incisive, IMC, Genus, Innovus

Credits / Reference : All rights & credits for the lab experiment belong to JNTUH,
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Note : Experiments are being made available for educational & informational purposes only.