UTB49(a) - Part-1: ASIC Design and Verification of Demultiplexer and Comparator (RTL-to-Netlist)

• Introduction to Demultiplexers and Comparators.
• Applications

Agenda:

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for Demultiplexer and Comparator.
• Test bench creation for Functional Simulation
• Coverage Analysis using IMC tool
• Formal Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Tools Used: Cadence Xcelium, IMC, Jasper Gold, Genus, Modus, Conformal LEC.

Credits / Reference: All rights & credits for the lab experiment belong to JNTU Hyderabad, This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.