Part-1: ASIC Design and Verification of I²C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist)

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for I2C
• Testbench creation for Functional Simulation
• Coverage Analysis of Testbench
• Formal Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

 

Tools Used : Cadence Incisive/ Xcelium, IMC, Jasper Gold, Genus, Modus, Conformal LEC.

Credits / Reference : All Rights & Credits belong to Centurion University Odisha, Southern Illinois University Edwardsville, etc.