Part-1: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist)

Prelude:

• Introduction to Shift Register
• Types of shift Register : SIPO,SISO,PIPO and PISO
• Introduction to Universal Shift Register
• Architecture and functional description of Universal Shift Register

 

Agenda:

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for Universal Shift Register
• Test bench creation for Functional Simulation
• Coverage Analysis using IMC tool
• Formal Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

• Tools Used: Cadence Xcelium, IMC, Jasper Gold, Genus, Modus, Conformal LEC.
• Credits / Reference: All rights & credits for the lab experiment belong to Anna University 2021 Regulation. This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.
• Note: Experiments are being made available for educational & informational purposes only.