Part-2: ASIC Physical Design and Verification of I²C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII)

Agenda :

Prelude: 

• Introduction to ASIC Physical Design, Verification and Sign-off
• Recap of I²C Front-end design and Report analysis

Main Session:

• I²C Netlist data preparation for Physical Design
• Sanity Checks
• Floor and Power Planning,
• Placement, CTS, & Routing
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

 

Tools Used : Innovus, Quantus, Tempus, Voltus, PVS, Conformal LEC and Xcelium.

Credits / Reference : All Rights & Credits belong to Centurion University Odisha, Southern Illinois University Edwardsville, etc.