About The Course

Physical design is the process of creating the layout of the IC. In this course, you will be able to understand the physical design of IC Layout flow from Netlist to GDSII.

In this internship, we'll guide you through the entire physical design process, starting from the netlist obtained from synthesis. You'll explore each step in detail, acquiring the skills needed to design layouts that adhere to the highest standards of performance and manufacturability.

What Will You Learn?

Physical design is based on a netlist which is the end result of the synthesis process. Main steps in physical design are Floor Planning, Power planning, Placement of all logical cells, scan chain reordering, Clock Tree Synthesis, Routing and ECO. During this process area, timing, power, design & technology constraints have to be met.

Key Features of the Course

• Introduction to Physical Design
• Floor Planning
• Clock Tree Synthesis
• Simulation and Debugging Techniques
• Certification and Technical Support
• Cadence EDA Tool Access*