UTB 38, Part 2 - Boolean Expression Implementation using CMOS Logic – Cadence Tool Flow

Prelude :

• Preview of Session-1
• Introduction to Euler's Path
• Stick diagram

 

Agenda :

• Layout Capture – Designing the Boolean Expression in Cadence Virtuoso
• Physical Verification –Setup and analysis of DRC and LVS using Assura.
• Post Layout simulation – Evaluating circuit behavior and performance
• Propagation Delay Calculation – Setting up and analyzing timing parameters
• Q&A Session

 

Tools Used:  Virtuoso Layout Editor, ADE L (Analog Design Environment L), Spectre Simulator, Assura.

Credits/Reference: All rights and credits for the lab experiment belong to the VTU 2022 Scheme. This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.

Note: Experiments are being made available for educational and informational purposes only.