Layout Design of PMOS, NMOS Transistors

Agenda:

• Layout Capture of CMOS (PMOS and NMOS)
• Accurate Physical Representation of Circuit Functionality
• Compliance with Design Rules (DRC)
• Optimized Area Utilization

• Tools Used: Virtuoso Layout Editor.
• Credits / Reference: All rights & credits for the lab experiment belong to Dr. A. P. J. Abdul Kalam Technical University, Lucknow. This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.
• Note: Experiments are being made available for educational & informational purposes only.