About the course

Implementation of XOR GATE Using Cadence EDA Tool

Prelude:

Introduction
Applications of XOR gate
Advantages and Challenges of CMOS XOR Gate

Agenda :

Schematic Capture and Simulation using Virtuoso Schematic Editor
Creating Layout Using Virtuoso Layout Editor
Physical Verification & Parasitic Extraction
Post layout Simulation
GDSII generation

Tools used :

Incisive/Xcelium
Genus
Conformal
Modus
Innovus
PVS

All rights & credits for the lab experiment belong to JNTU, Hyderabad. This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.
Note: Experiments are being made available for educational & informational purposes only.

Course Details

About Abhiyantha

Abhiyantha Centre for Advanced Learning in Engineering and Technology was set up to support engineers, freshers and experienced, in preparing them to be industry-ready and enhancing their professional growth.

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FAQs

Who is eligible for Internships program?

UG/PG graduates
UG/PG Final year students

What is the contact for additional queries/questions on Internship Program

Write to us – ask@abhiyantha.com, info@abhiyantha.com
Give a missed call – +91 8042171597
Connect to us on WhatsApp – +91 9513400942

If I change my mind, can I discontinue the course and get a Refund?

Yes, Refund can be initiated only within 3 days of enrollment.

UTB15 - Implementation of XOR GATE Using Cadence EDA Tool

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About the course

Course Details

About Abhiyantha

Reviews and Testimonials

FAQs

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UTB15 - Implementation of XOR GATE Using Cadence EDA Tool

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Reviews and Testimonials

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