Design & Implementation of 1-Bit Full Adder using Cadence Tools:

Prelude : 

• Introduction
• Schematic Architectures of Full adder
• Qualitative Analysis of the cost of implementation
• Design problem-statement

 

Agenda :

• Schematic Capture and Simulation using Virtuoso Schematic Editor
• Delay Estimation using calculator
• Creating Layout Using Virtuoso Layout Editor
• Physical Verification & Parasitic Extraction
• Post layout Simulation