Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist)

Prelude :

• Introduction to FIFO
• Functional logic description of FIFO

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for FIFO
• Testbench creation for Functional Simulation
• Coverage Analysis of Testbench
• Formal Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

 

Tools used :

• Cadence Incisive/ Xcelium
• IMC
• Jasper Gold
• Genus
• Modus
• Conformal LEC