Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII)

Prelude :

• Introduction to ASIC Physical Design, Verification and Sign-off
• Recap of FIFO Front-end design and Report analysis

Agenda :

• FIFO Netlist data preparation for Physical Design 
• Sanity Checks
• Floor and Power Planning,
• Placement, CTS, & Routing
• Timing and Power Analysis 
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

 

Tools used :

• Innovus
• Quantus
• Tempus, Voltus
• PVS
• Conformal LEC
• Xcelium