Part-1: ASIC Design and Verification of Design of 4 bit binary to gray converter (RTL-to-Netlist)

Prelude:

• Introduction to Different Binary Codes
• Application of Gray Code
• Architecture and functional description of 4-bit Binary to Gray Converter

Agenda:

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for 4-bit Binary to Gray Converter
• Test bench creation for Functional Simulation
• Coverage Analysis using IMC tool
• Formal Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)
• Tools Used: Cadence Xcelium, IMC, Jasper Gold, Genus, Modus, Conformal LEC.
• Credits / Reference: All rights & credits for the lab experiment belong to R22 - EC605PC: CMOS VLSI Design Laboratory,