Part-2: ASIC Design and Verification of Design of 4 bit binary to gray converter

Prelude:

• Review of Part-1: ASIC Design and Verification of Design

Agenda:

• Introduction to ASIC Physical Design, Verification and Sign-off
• Recap of Front-end design and Report analysis
• Netlist data preparation for Physical Design
• Sanity Checks
• Floor and Power Planning,
• Placement & Routing
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Credits / Reference: All rights & credits for the lab experiment belong to R22 - EC605PC: CMOS VLSI Design Laboratory. This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.