Design and Implementation of a 4:1 Multiplexer using Cadence Tools - Part 2

Prelude:

• Review of schematic capture of 4:1 Multiplexer (PART-I)

Agenda:

• Implementation of Layout for Basic logic gates (AND, INVERTER, OR)
• Implementation of Layout for 4:1 Multiplexer
• Physical Verification & Parasitic Extraction
• Post layout Simulation
• GDSII Extraction
  
  Tools Used: Virtuoso Schematic Editor, Spectre Simulator
  Credits / Reference: All rights & credits for the lab experiment belong to Dr. A. P. J. Abdul Kalam Technical University, Lucknow, This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.