UTB47(a) - Part-1: Full Adder circuit using Three Modeling StylesPrelude:

• Introduction to Full Adder using 3 Modelling Styles.
• Architecture and functional description of Full Adder

Agenda:

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for Full Adder Circuit using 3 modelling styles
• Test bench creation for Functional Simulation
• Coverage Analysis using IMC tool
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Tools Used: Cadence Xcelium, IMC, Genus, Conformal LEC.

Credits / Reference: All rights & credits for the lab experiment belong to JNTU Hyderabad, This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.