UTB48B - Part-2 : ASIC Design and Verification of 8:3 Encoder (RTL-to-Netlist)

Agenda :

• Review of Part-1 : Introduction to 8:3 Encoder
• Introduction to ASIC Physical Design, Verification and Sign-off
• Recap of 8:3 Encoder Front-end design and Report analysis
• 8:3 Encoder netlist data preparation for Physical Design
• Sanity Checks
• Floor and Power Planning,
• Placement, CTS, & Routing
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Final GDSII file generation

 

Tools used: Innovus, Quantus, Voltus, Conformal LEC, Xcelium.

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Note: Experiments are being made available for educational & informational purposes only.