Design and Implementation of D-Latch using Cadence EDA Tools

Prelude:

• Introduction to Sequential Logic
• Combinational vs Sequential Circuits
• D-Latch Architecture and Operation
• Truth Table and Characteristic Equation
• CMOS Inverter and Transmission Gat

Agenda:

• Schematic Capture of D Latch Using Virtuoso Schematic Editor
• Schematic and Symbol Implementation of D-Latch
• Transient Analysis using Spectre Simulator
• Layout Implementation of D-Latch
• DRC and LVS Verification
• Post-Layout Simulation Analysis
  
  Tools Used: Virtuoso, Spectre, Assura and Quantus.
  Credits / Reference: All rights & credits for the lab experiment belong to JNTU Syllabus. This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.
  Note: Experiments are being made available for educational & informational purposes only.