Sort By

University Tech Bytes

UTB48a - Part-1 : ASIC Design and Verification of 8:3 Encoder cover

UTB48a - Part-1 : ASIC Design and Verification of 8:3 Encoder

Rakesh

UTB49(a) - Part-1: ASIC Design and Verification of Demultiplexer and Comparator (RTL-to-Netlist) cover

UTB49(a) - Part-1: ASIC Design and Verification of Demultiplexer and Comparator (RTL-to-Netlist)

Sanjay

UTB48b - Part-2 : ASIC Design and Verification of 8:3 Encoder (RTL-to-Netlist) cover

UTB48b - Part-2 : ASIC Design and Verification of 8:3 Encoder (RTL-to-Netlist)

Rakesh

UTB47(b) - Part-2: Full Adder circuit using Three Modeling Styles cover

UTB47(b) - Part-2: Full Adder circuit using Three Modeling Styles

Sanjay

UTB47(a) - Part-1: Full Adder circuit using Three Modeling Styles cover

UTB47(a) - Part-1: Full Adder circuit using Three Modeling Styles

Sanjay

UTB46(b) - Design and Implementation of a 4:1 Multiplexer using Cadence Tools cover

UTB46(b) - Design and Implementation of a 4:1 Multiplexer using Cadence Tools

Sanjay

UTB46(a) - Design and Implementation of a 4:1 Multiplexer using Cadence Tools cover

UTB46(a) - Design and Implementation of a 4:1 Multiplexer using Cadence Tools

Sanjay

UTB45 (B) - Part-2: ASIC Design and Verification of Design of 4 bit binary to gray converter cover

UTB45 (B) - Part-2: ASIC Design and Verification of Design of 4 bit binary to gray converter

Sanjay

UTB44 (b) - Part-2 - Design & Implementation of 3:8 Decoder using Cadence Tool cover

UTB44 (b) - Part-2 - Design & Implementation of 3:8 Decoder using Cadence Tool

Sanjay

UTB44 (a) - Part-1 - Design & Implementation of 3:8 Decoder using Cadence Tool cover

UTB44 (a) - Part-1 - Design & Implementation of 3:8 Decoder using Cadence Tool

Sanjay

UTB45 (a) - Part-1: ASIC Design and Verification of Design of 4 bit binary to gray converter (RTL-to-Netlist) cover

UTB45 (a) - Part-1: ASIC Design and Verification of Design of 4 bit binary to gray converter (RTL-to-Netlist)

Sanjay

UTB43 (b) - Part-2: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist) cover

UTB43 (b) - Part-2: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist)

Sanjay

UTB43 (a) - Part-1: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist) cover

UTB43 (a) - Part-1: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist)

Sanjay

Mech UTB25 - CFD simulation of flow over backward facing step cover

Mech UTB25 - CFD simulation of flow over backward facing step

Dheeraj Mathew Paulson

Mech UTB24 - CFD Flow around an Airfoil cover

Mech UTB24 - CFD Flow around an Airfoil

Dheeraj Mathew paulson

UTB 41(b) - Part 2: Designing and Implementing of Half-Adder using Cadence EDA Tools cover

UTB 41(b) - Part 2: Designing and Implementing of Half-Adder using Cadence EDA Tools

Sanjay