Sort By

Recording Internship

Design & Verification using Verilog - DV - STD cover

Design & Verification using Verilog - DV - STD

Abhiyantha

₹12999 ₹4719

System Verilog Based Verification - SV - STD cover

System Verilog Based Verification - SV - STD

Abhiyantha

₹9999 ₹4719

ASIC Synthesis and STA - STD cover

ASIC Synthesis and STA - STD

Entuple Technologies

₹15999 ₹4719

Physical Design and Verification - PD STD cover

Physical Design and Verification - PD STD

Dr. Mamidi Nagaraju, Navaneetha Krishnan

₹15999 ₹4719