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VLSI
UTB46 - Design and Implementation of a 4:1 Multiplexer using Cadence Tools
Sanjay
UTB45 (B) - Part-2: ASIC Design and Verification of Design of 4 bit binary to gray converter
Sanjay
UTB44 (b) - Part-2 - Design & Implementation of 3:8 Decoder using Cadence Tool
Sanjay
UTB44 (a) - Part-1 - Design & Implementation of 3:8 Decoder using Cadence Tool
Sanjay
UTB43 (a) - Part-1: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist)
Sanjay
UTB 41(b) - Part 2: Designing and Implementing of Half-Adder using Cadence EDA Tools
Sanjay
UTB 42 - Layout Design of PMOS, NMOS Transistors
Bhanushree
UTB 41(a) - Part 1: Designing and Implementing of Half-Adder using Cadence EDA Tools
Sanjay
UTB 40 - Design and Simulation of Regulator circuit with PCB Implementation using Cadence OrCAD EDA
Kamlesh Kumar
UTB 39 - Design of 2-To-4 Decoder Using Cadence EDA
Sanjay
UTB 38 - Part 2 - Boolean Expression Implementation using CMOS Logic Cadence Tool Flow
Shivaprasad B K
UTB 38 - Part 1 - Boolean Expression Implementation using CMOS Logic Cadence Tool Flow
Shivaprasad B K
UTB 37 - Part-2: ASIC Physical Design and Implementation Shift & add Multiplier using Cadence EDA Tools
Shivaprasad B K
UTB 37 - Part-1: ASIC Design & Verification of Shift & Add Multiplier using Cadence EDA Tools
Shivaprasad B K
UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII)
Navaneetha Krishnan
UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist)
Ashwini H, Pooja C
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