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UTB 38 - Part 1 - Boolean Expression Implementation using CMOS Logic Cadence Tool Flow cover

UTB 38 - Part 1 - Boolean Expression Implementation using CMOS Logic Cadence Tool Flow

Shivaprasad B K

UTB 37 - Part-2: ASIC Physical Design and Implementation Shift & add Multiplier using Cadence EDA Tools cover

UTB 37 - Part-2: ASIC Physical Design and Implementation Shift & add Multiplier using Cadence EDA Tools

Shivaprasad B K

UTB 37 - Part-1: ASIC Design & Verification of Shift & Add Multiplier using Cadence EDA Tools cover

UTB 37 - Part-1: ASIC Design & Verification of Shift & Add Multiplier using Cadence EDA Tools

Shivaprasad B K

UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII) cover

UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII)

Navaneetha Krishnan

UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist) cover

UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist)

Ashwini H, Pooja C

UTB35 - Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII) cover

UTB35 - Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII)

Navaneetha Krishnan, Pooja C

UTB35 - Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist) cover

UTB35 - Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist)

Ashwini H, Pooja C

UTB34(b) - Part-2: ASIC Physical Design and Verification (Netlist-to-GDSII) of a Mod-N(Mod-10) Counter cover

UTB34(b) - Part-2: ASIC Physical Design and Verification (Netlist-to-GDSII) of a Mod-N(Mod-10) Counter

Dr Mamidi Nagaraju, Ashwini H

UTB33(b) - Part-2: ASIC Physical Design and Implemetation of SPI Protocol (Netlist-to-GDSII) cover

UTB33(b) - Part-2: ASIC Physical Design and Implemetation of SPI Protocol (Netlist-to-GDSII)

Dr Mamidi Nagaraju

UTB33(a) - Part 1: ASIC Design and Verification of SPI Communication Protocol using Cadence EDA Tools (RTL-to-Netlist) cover

UTB33(a) - Part 1: ASIC Design and Verification of SPI Communication Protocol using Cadence EDA Tools (RTL-to-Netlist)

Dr Mamidi Nagaraju

UTB32 - Design & Implementation of 1-Bit Full Adder using Cadence Tools cover

UTB32 - Design & Implementation of 1-Bit Full Adder using Cadence Tools

Dr Mamidi Nagaraju

UTB31 (b) - Part-2: Physical Design and Verification of PWM Generator (Netlist-to-GDSII) cover

UTB31 (b) - Part-2: Physical Design and Verification of PWM Generator (Netlist-to-GDSII)

Dr Mamidi Nagaraju

UTB31 (a) - Part-1: ASIC Design and Verification of PWM Generator (RTL-to-Netlist) cover

UTB31 (a) - Part-1: ASIC Design and Verification of PWM Generator (RTL-to-Netlist)

Dr Mamidi Nagaraju, Ashwini H

UTB30 - Design & Implementation Of Two Input CMOS NOR Gate using Cadence EDA Tools cover

UTB30 - Design & Implementation Of Two Input CMOS NOR Gate using Cadence EDA Tools

Shivaprasad B K

UTB29 Part-2: Back-end ASIC Implementation of Chip-Level MAC Unit (Netlist-to-GDSII) cover

UTB29 Part-2: Back-end ASIC Implementation of Chip-Level MAC Unit (Netlist-to-GDSII)

Dr Mamidi Nagaraju, Ashwini H

UTB29 Part:1 -ASIC Design and Verification of MAC Unit (RTL-to-Netlist) cover

UTB29 Part:1 -ASIC Design and Verification of MAC Unit (RTL-to-Netlist)

Dr Mamidi Nagaraju, Ashwini H