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UTB48a - Part-1 : ASIC Design and Verification of 8:3 Encoder cover

UTB48a - Part-1 : ASIC Design and Verification of 8:3 Encoder

Rakesh

UTB49(a) - Part-1: ASIC Design and Verification of Demultiplexer and Comparator (RTL-to-Netlist) cover

UTB49(a) - Part-1: ASIC Design and Verification of Demultiplexer and Comparator (RTL-to-Netlist)

Sanjay

UTB48b - Part-2 : ASIC Design and Verification of 8:3 Encoder (RTL-to-Netlist) cover

UTB48b - Part-2 : ASIC Design and Verification of 8:3 Encoder (RTL-to-Netlist)

Rakesh

UTB47(b) - Part-2: Full Adder circuit using Three Modeling Styles cover

UTB47(b) - Part-2: Full Adder circuit using Three Modeling Styles

Sanjay

UTB47(a) - Part-1: Full Adder circuit using Three Modeling Styles cover

UTB47(a) - Part-1: Full Adder circuit using Three Modeling Styles

Sanjay

UTB46(b) - Design and Implementation of a 4:1 Multiplexer using Cadence Tools cover

UTB46(b) - Design and Implementation of a 4:1 Multiplexer using Cadence Tools

Sanjay

UTB46(a) - Design and Implementation of a 4:1 Multiplexer using Cadence Tools cover

UTB46(a) - Design and Implementation of a 4:1 Multiplexer using Cadence Tools

Sanjay

UTB45 (B) - Part-2: ASIC Design and Verification of Design of 4 bit binary to gray converter cover

UTB45 (B) - Part-2: ASIC Design and Verification of Design of 4 bit binary to gray converter

Sanjay

UTB44 (b) - Part-2 - Design & Implementation of 3:8 Decoder using Cadence Tool cover

UTB44 (b) - Part-2 - Design & Implementation of 3:8 Decoder using Cadence Tool

Sanjay

UTB44 (a) - Part-1 - Design & Implementation of 3:8 Decoder using Cadence Tool cover

UTB44 (a) - Part-1 - Design & Implementation of 3:8 Decoder using Cadence Tool

Sanjay

UTB43 (a) - Part-1: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist) cover

UTB43 (a) - Part-1: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist)

Sanjay

UTB 41(b) - Part 2: Designing and Implementing of Half-Adder using Cadence EDA Tools cover

UTB 41(b) - Part 2: Designing and Implementing of Half-Adder using Cadence EDA Tools

Sanjay

UTB 42 - Layout Design of PMOS, NMOS Transistors cover

UTB 42 - Layout Design of PMOS, NMOS Transistors

Bhanushree

UTB 41(a) - Part 1: Designing and Implementing of Half-Adder using Cadence EDA Tools cover

UTB 41(a) - Part 1: Designing and Implementing of Half-Adder using Cadence EDA Tools

Sanjay

UTB 40 - Design and Simulation of Regulator circuit with PCB Implementation using Cadence OrCAD EDA cover

UTB 40 - Design and Simulation of Regulator circuit with PCB Implementation using Cadence OrCAD EDA

Kamlesh Kumar

UTB 39 - Design of 2-To-4 Decoder Using Cadence EDA cover

UTB 39 - Design of 2-To-4 Decoder Using Cadence EDA

Sanjay