Sort By

VLSI

UTB43 (a) - Part-1: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist) cover

UTB43 (a) - Part-1: ASIC Design and Verification of Universal Shift Register (RTL-to-Netlist)

Sanjay

UTB 41(b) - Part 2: Designing and Implementing of Half-Adder using Cadence EDA Tools cover

UTB 41(b) - Part 2: Designing and Implementing of Half-Adder using Cadence EDA Tools

Sanjay

UTB 42 - Layout Design of PMOS, NMOS Transistors cover

UTB 42 - Layout Design of PMOS, NMOS Transistors

Bhanushree

UTB 41(a) - Part 1: Designing and Implementing of Half-Adder using Cadence EDA Tools cover

UTB 41(a) - Part 1: Designing and Implementing of Half-Adder using Cadence EDA Tools

Sanjay

UTB 40 - Design and Simulation of Regulator circuit with PCB Implementation using Cadence OrCAD EDA cover

UTB 40 - Design and Simulation of Regulator circuit with PCB Implementation using Cadence OrCAD EDA

Kamlesh Kumar

UTB 39 - Design of 2-To-4 Decoder Using Cadence EDA cover

UTB 39 - Design of 2-To-4 Decoder Using Cadence EDA

Sanjay

UTB 38 - Part 2 - Boolean Expression Implementation using CMOS Logic Cadence Tool Flow cover

UTB 38 - Part 2 - Boolean Expression Implementation using CMOS Logic Cadence Tool Flow

Shivaprasad B K

UTB 38 - Part 1 - Boolean Expression Implementation using CMOS Logic Cadence Tool Flow cover

UTB 38 - Part 1 - Boolean Expression Implementation using CMOS Logic Cadence Tool Flow

Shivaprasad B K

UTB 37 - Part-2: ASIC Physical Design and Implementation Shift & add Multiplier using Cadence EDA Tools cover

UTB 37 - Part-2: ASIC Physical Design and Implementation Shift & add Multiplier using Cadence EDA Tools

Shivaprasad B K

UTB 37 - Part-1: ASIC Design & Verification of Shift & Add Multiplier using Cadence EDA Tools cover

UTB 37 - Part-1: ASIC Design & Verification of Shift & Add Multiplier using Cadence EDA Tools

Shivaprasad B K

UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII) cover

UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII)

Navaneetha Krishnan

UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist) cover

UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist)

Ashwini H, Pooja C

UTB35 - Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII) cover

UTB35 - Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII)

Navaneetha Krishnan, Pooja C

UTB35 - Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist) cover

UTB35 - Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist)

Ashwini H, Pooja C

UTB34(b) - Part-2: ASIC Physical Design and Verification (Netlist-to-GDSII) of a Mod-N(Mod-10) Counter cover

UTB34(b) - Part-2: ASIC Physical Design and Verification (Netlist-to-GDSII) of a Mod-N(Mod-10) Counter

Dr Mamidi Nagaraju, Ashwini H

UTB33(b) - Part-2: ASIC Physical Design and Implemetation of SPI Protocol (Netlist-to-GDSII) cover

UTB33(b) - Part-2: ASIC Physical Design and Implemetation of SPI Protocol (Netlist-to-GDSII)

Dr Mamidi Nagaraju